AT90S8515A-4JC Atmel, AT90S8515A-4JC Datasheet - Page 40
![IC MCU 8K FLSH 4MHZ LV 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
AT90S8515A-4JC
Manufacturer Part Number
AT90S8515A-4JC
Description
IC MCU 8K FLSH 4MHZ LV 44PLCC
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheets
1.AT90S8515-4AC.pdf
(112 pages)
2.AT90S8515-4AC.pdf
(4 pages)
3.AT90S8515-4AC.pdf
(4 pages)
Specifications of AT90S8515A-4JC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Timer/Counter1 in PWM Mode
40
AT90S8515
The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the
main program and interrupt routines perform access to registers using TEMP, interrupts
must be disabled during access from the main program (and from interrupt routines if
interrupts are allowed from within interrupt routines).
When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A
(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit,
free-running, glitch-free and phase-correct PWM with outputs on the PD5(OC1A) and
OC1B pins. Timer/Counter1 acts as an up/down counter, counting up from $0000 to
TOP (see Table 11), where it turns and counts down again to zero before the cycle is
repeated. When the counter value matches the contents of the 10 least significant bits of
OCR1A or OCR1B, the PD5(OC1A)/OC1B pins are set or cleared according to the set-
tings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control
Register (TCCR1A). Refer to Table 12 for details.
Table 11. Timer TOP Values and PWM Frequency
Table 12. Compare1 Mode Select in PWM Mode
Note:
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written,
are transferred to a temporary location. They are latched when Timer/Counter1 reaches
the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the
event of an unsynchronized OCR1A/OCR1B write. See Figure 32 for an example.
COM1X1
0
0
1
1
PWM Resolution
X = A or B
COM1X0
10-bit
8-bit
9-bit
0
1
0
1
Not connected
Not connected
Cleared on compare match, up-counting. Set on compare match,
down-counting (non-inverted PWM).
Cleared on compare match, down-counting. Set on compare match,
up-counting (inverted PWM).
Effect on OCX1
Timer TOP Value
$03FF(1023)
$00FF (255)
$01FF (511)
Frequency
f
f
f
TCK1
TCK1
TCK1
/1022
/2046
/510
0841G–09/01