AT90S4433-8AC Atmel, AT90S4433-8AC Datasheet - Page 53

• Manufacturer Part Number: AT90S4433-8AC
• Description: IC MCU 4K FLSH 8MHZ A/D 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S4433-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART
Data Transmission
1042H–AVR–04/03
The AT90S4433 features a full duplex (separate Receive and Transmit Registers) Uni-
versal Asynchronous Receiver and Transmitter (UART). The main features are:
•
•
•
•
•
•
•
•
•
A block schematic of the UART Transmitter is shown in Figure 40.
Figure 40. UART Transmitter
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register (UDR). Data is transferred from UDR to the Transmit Shift Register when:
•
•
When data is transferred from UDR to the Shift Register, the UDRE (UART Data Regis-
ter Empty) bit in the UART Control and Status Register A, UCSRA, is set. When this bit
is set (one), the UART is ready to receive the next character. At the same time as the
Baud Rate Generator Generates any Baud Rate
High Baud Rates at Low XTAL Frequencies
8 or 9 Bits Data
Noise Filtering
Overrun Detection
Framing Error Detection
False Start Bit Detection
Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
Multi-processor Communication Mode
A new character has been written to UDR after the stop bit from the previous
character has been shifted out. The Shift Register is loaded immediately.
A new character has been written to UDR before the stop bit from the previous
character has been shifted out. The Shift Register is loaded when the stop bit of the
character currently being transmitted has been shifted out.
REGISTER B (UCSRB)
UART CONTROL
AND STAUS
REGISTER A (UCSRA)
UART CONTROL
AND STAUS
AT90S/LS4433
53