PIC16C84-10I/P Microchip Technology, PIC16C84-10I/P Datasheet - Page 33

• Manufacturer Part Number: PIC16C84-10I/P
• Description: IC MCU EEPM 1K 10MHZ IT 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-10I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

7.5
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
Generally the EEPROM write failure will be a bit which
was written as a '1', but reads back as a '0' (due to
leakage off the bit).
EXAMPLE 7-1:
READ
;
; Is the value written (in W reg) and
;
;
TABLE 7-1
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
1997 Microchip Technology Inc.
Address
08h
09h
88h
89h
BCF
:
:
MOVF
BSF
BSF
BCF
read (in EEDATA) the same?
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO
:
:
Write Verify
used by Data EEPROM.
STATUS, RP0 ; Bank 0
EEDATA, W
STATUS, RP0 ; Bank 1
EECON1, RD
STATUS, RP0 ; Bank 0
WRITE_ERR
Name
EECON1
EECON2
EEDATA
EEADR
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
WRITE VERIFY
EEPROM data register
EEPROM address register
EEPROM control register 2
Bit 7
—
; Any code can go here
;
; Must be in Bank 0
; YES, Read the
;
;
; Is difference 0?
; NO, Write error
; YES, Good write
; Continue program
value written
Bit 6
—
Bit 5
—
Bit 4
EEIF
WRERR
Bit 3
7.6
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
7.7
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data
EEPROM.
For ROM devices, there are two code protection bits
(Section 8.1). One for the ROM program memory and
one for the Data EEPROM memory.
7.8
WREN
Note:
Bit 2
Protection Against Spurious Writes
Data EEPROM Operation during Code
Protect
Power Consumption Considerations
It is recommended that the EEADR<7:6>
bits be cleared. When either of these bits is
set, the maximum I
higher than when both are cleared. The
specification is 400 A. With EEADR<7:6>
cleared, the maximum is approximately
150 A.
Timer
Bit 1
WR
(72
Bit 0
RD
ms
PIC16C84
xxxx xxxx
xxxx xxxx
---0 x000
---- ----
DD
Power-on
Value on
duration)
Reset
for the device is
DS30445C-page 33
other resets
Value on all
uuuu uuuu
uuuu uuuu
---0 q000
---- ----
prevents