PIC16C84-10I/P Microchip Technology, PIC16C84-10I/P Datasheet - Page 19

• Manufacturer Part Number: PIC16C84-10I/P
• Description: IC MCU EEPM 1K 10MHZ IT 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-10I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

5.0
The PIC16C84 has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate func-
tion for other features on the device.
5.1
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
FIGURE 5-1:
driver in a hi-impedance mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The RA4 pin is multiplexed with the TMR0 clock input.
Data
bus
WR
Port
WR
TRIS
Note: I/O pins have protection diodes to V
RD PORT
1997 Microchip Technology Inc.
I/O PORTS
PORTA and TRISA Registers
D
D
Data Latch
TRIS Latch
CK
CK
BLOCK DIAGRAM OF PINS
RA3:RA0
Q
Q
Q
Q
RD TRIS
Q
EN
D
TTL
input
buffer
DD
V
V
P
N
SS
DD
and V
SS
I/O pin
.
EXAMPLE 5-1:
CLRF
BSF
MOVLW
MOVWF
FIGURE 5-2:
Note:
Data
bus
WR
TRIS
WR
PORT
RD PORT
Note: I/O pin has protection diodes to V
TMR0 clock input
PORTA
STATUS, RP0
0x0F
TRISA
For
operating below 500 kHz, the device may
generate a spurious internal Q-clock when
PORTA<0> switches state. This does not
occur with an external clock in RC mode.
To avoid this, the RA0 pin should be kept
static, i.e. in input/output mode, pin RA0
should not be toggled.
TRIS Latch
Data Latch
D
D
CK
CK
crystal
BLOCK DIAGRAM OF PIN RA4
RD TRIS
INITIALIZING PORTA
Q
Q
Q
Q
; Initialize PORTA by
; setting output
; data latches
; Select Bank 1
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA4 as outputs
; TRISA<7:5> are always
; read as '0'.
oscillator
PIC16C84
Q
EN
Schmitt
Trigger
input
buffer
EN
D
DS30445C-page 19
V
N
SS
configurations
SS
only.
RA4 pin