DS87C520-QNL+T&R Maxim Integrated Products, DS87C520-QNL+T&R Datasheet - Page 5

• Manufacturer Part Number: DS87C520-QNL+T&R
• Description: IC MCU EPROM/ROM 33MH IND 44PLCC
• Manufacturer: Maxim Integrated Products
• Series: 87Cr

Specifications of DS87C520-QNL+T&R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC, 44-PLCC
• Processor Series: DS87C520
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 44PLCC
• Device Core: 8051
• Family Name: 87C
• Maximum Speed: 33 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIN DESCRIPTION (continued)
DIP
30
39
38
37
36
35
34
33
32
1
2
3
4
5
6
7
8
PLCC
33
43
42
41
40
39
38
37
36
2
3
4
5
6
7
8
9
PIN
TQFP
27
37
36
35
34
33
32
31
30
40
41
42
43
44
1
2
3
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
NAME
ALE
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
Address Latch Enable Output. The ALE functions as a clock to
latch the external address LSB from the multiplexed address/data bus
on Port 0. This signal is commonly connected to the latch enable of an
external 373 family transparent latch. ALE has a pulse width of 1.5
XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced
high when the DS87C520/DS83C520 are in a reset condition. ALE
can also be disabled and forced high by writing ALEOFF = 1
(PMR.2). ALE operates independently of ALEOFF during external
memory accesses.
Port 0 (AD0–7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O
port. As an alternate function Port 0 can function as the multiplexed
address/data bus to access off-chip memory. During the time when
ALE is high, the LSB of a memory address is presented. When ALE
falls to a logic 0, the port transitions to a bidirectional data bus. This
bus is used to read external ROM and read/write external RAM
memory or peripherals. When used as a memory bus, the port
provides active high drivers. The reset condition of Port 0 is tri-state.
Pullup resistors are required when using Port 0 as an I/O port.
Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port
and an alternate functional interface for Timer 2 I/O, new External
Interrupts, and new Serial Port 1. The reset condition of Port 1 is with
all bits at a logic 1. In this state, a weak pullup holds the port high.
This condition also serves as an input state; a weak pullup holds the
port high. This condition also serves as an input mode, since any
external circuit that writes to the port will overcome the weak pullup.
When software writes a 0 to any port pin, the DS87C520/DS83C520
will activate a strong pulldown that remains on until either a 1 is
written or a reset occurs. Writing a 1 after the port has been at 0 will
cause a strong transition driver to turn on, followed by a weaker
sustaining pullup. Once the momentary strong driver turns off, the
port again becomes the output high (and input) state. The alternate
modes of Port 1 are out-lines as follows.
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
5 of 43
Alternate
T2
T2EX
RXD1
TXD1
INT2
INT3
INT4
INT5
External I/O for Timer/Counter 2
Serial Port 1 Input
Serial Port 1 Output
External Interrupt 2 (Positive Edge Detect)
External Interrupt 3 (Negative Edge Detect)
External Interrupt 4 (Positive Edge Detect)
External Interrupt 5 (Negative Edge Detect)
EX Timer/Counter 2 Capture/Reload Trigger
FUNCTION
Function