DS87C520-QNL+T&R Maxim Integrated Products, DS87C520-QNL+T&R Datasheet - Page 43

IC MCU EPROM/ROM 33MH IND 44PLCC

DS87C520-QNL+T&R

Manufacturer Part Number
DS87C520-QNL+T&R
Description
IC MCU EPROM/ROM 33MH IND 44PLCC
Manufacturer
Maxim Integrated Products
Series
87Cr
Datasheet

Specifications of DS87C520-QNL+T&R

Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
EBI/EMI, SIO, UART/USART
Peripherals
Power-Fail Reset, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LCC, 44-PLCC
Processor Series
DS87C520
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Package
44PLCC
Device Core
8051
Family Name
87C
Maximum Speed
33 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
DATA SHEET REVISION SUMMARY
REVISION
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No
110195
022097
070698
070300
040104
070505
091605
022207
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0
Preliminary release.
1) Update ALE pin description.
2) Add note pertaining to erasure window.
3) Add note pertaining to internal MOVX SRAM.
4) Change Note 10 from RST = 5.5V to RST = V
5) Change serial port mode 0 timing diagram label from t
1) Update PMM operating current estimates
2) Added note to clarify I
3) Added note to prevent accidental corruption of Watchdog Timer count while changing counter length.
4) Changed minimum oscillator frequency to 1MHz when using external crystal.
5) Changed RST pulldown resistance from 170kto 200kmaximum.
6) Corrected “Data memory write with stretch” diagrams to show falling edge of ALE coincident with
1) Corrected P0 pinout description for TQFP package.
2) Clarified point at which reset delay begins.
1) Removed “Preliminary” status.
2) Soldering temperature parameter now references JEDEC specification.
3) Added note to absolute maximums clarifying voltages referenced to ground.
4) Updated I
5) Added note clarifying DC electrical test conditions.
6) Added note clarifying V
7) Updated AC and MOVX electrical characteristics with final characterization values.
Added t
1) Added Pb-free/RoHS-compliant part numbers to Ordering Information table.
2) Deleted the “A” from the IPC/JEDEC J-STD-020 specification in the Absolute Maximum Ratings.
1) In DC Electrical Characteristics table, added separate specification for DS83C520 V
2) Changed V
1) (Page 30) In the Absolute Maximum Ratings table, changed the operating range from 0C to +70C to
2) (Page 33) In the MOVX Characteristics table, added Note 2 and changed t
-40C to +85C (correction for typographical error; this does not reflect a change in the device or device
testing).
Note 2.
rising edge of C3 clock.
AVLL2
specification and corrected MOVX timing diagrams to show t
CC
RST
, I
IDLE
max to from 4.25V to 4.275V for DS83C520 value.
, I
STOP
IL
, I
OH3
specification.
SPBG
specification applies to first clock cycle following the transition.
© 2007 Maxim Integrated Products
, I
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
IL
, and I
43 of 43
42 of 42
TL
DESCRIPTION
to incorporate errata conditions.
CC
.
QVXL
to t
QVXH
.
AVLL2
RLAZ
instead of t
max from Note 1 to
PFW
.
AVLL
.

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