SAF-XC161CS-32F20F BB-A Infineon Technologies, SAF-XC161CS-32F20F BB-A Datasheet - Page 44
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
SAF-XC161CS-32F20F BB-A
Manufacturer Part Number
SAF-XC161CS-32F20F BB-A
Description
IC MCU 16BIT FLASH 144-TQFP
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC161CS-32F20F_BB-A.pdf
(87 pages)
Specifications of SAF-XC161CS-32F20F BB-A
Core Processor
C166SV2
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
99
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 12x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
ASC, CAN, IIC, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
99
Number Of Timers
9
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
SP000224541
3.10
The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial
communication with other microcontrollers, processors, terminals or external peripheral
components. They are upward compatible with the serial ports of the Infineon 8-bit
microcontroller families and support full-duplex asynchronous communication and half-
duplex synchronous communication. A dedicated baud rate generator with a fractional
divider precisely generates all standard baud rates without oscillator tuning. For
transmission, reception, error handling, and baudrate detection 5 separate interrupt
vectors are provided.
In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted
or received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to
115.2 kbit/s with fixed or programmable IrDA pulse width are supported.
In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift
clock which is generated by the ASC0/1. The LSB is always shifted first.
In both modes, transmission and reception of data is FIFO-buffered. An autobaud
detection unit allows to detect asynchronous data frames with its baudrate and mode
with automatic initialization of the baudrate generator and the mode control bits.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
Summary of Features
•
•
•
•
•
Data Sheet
Full-duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking
– Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)
– Multiprocessor mode for automatic address/data byte detection
– Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)
– Loop-back capability
– Auto baudrate detection
Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)
Buffered transmitter/receiver with FIFO support (8 entries per direction)
Loop-back option available for testing purposes
Interrupt generation on transmitter buffer empty condition, last bit transmitted
condition, receive buffer full condition, error condition (frame, parity, overrun error),
start and end of an autobaud detection
Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)
42
Functional Description
XC161CS-32F
Derivatives
V1.2, 2006-08