SAK-XC2785X-72F80L AA Infineon Technologies, SAK-XC2785X-72F80L AA Datasheet - Page 128
SAK-XC2785X-72F80L AA
Manufacturer Part Number
SAK-XC2785X-72F80L AA
Description
IC MCU 32BIT FLASH 144-LQFP
Manufacturer
Infineon Technologies
Series
XC27x5Xr
Datasheet
1.SAK-XC2785X-104F80L_AA.pdf
(136 pages)
Specifications of SAK-XC2785X-72F80L AA
Core Processor
C166SV2
Core Size
16/32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
116
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000448086
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Table 38
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
TDO valid
after TCK falling edge
TDO high imped. to valid
from TCK falling edge
TDO valid to high imped.
from TCK falling edge
TDO hold after
TCK falling edge
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Figure 28
Data Sheet
0.5
V
DDP
JTAG Interface Timing Parameters for Lower Voltage Range
Test Clock Timing (TCK)
1)
1)
2)3)
1)
t
2
Symbol
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
18
t
1
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
t
3
Min.
50
16
16
–
–
6
6
–
–
–
5
XC2000 Family Derivatives / Base Line
128
Values
Typ.
–
–
–
–
–
–
–
32
32
32
–
t
5
Max.
–
–
–
8
8
–
–
36
36
36
–
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Electrical Parameters
t
4
Test Condition
MC_JTAG_TCK
V2.0, 2009-03
XC2785X
0.9
0.1
V
V
DDP
DDP
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