SAK-XC2287-96F80L AC Infineon Technologies, SAK-XC2287-96F80L AC Datasheet - Page 112

• Manufacturer Part Number: SAK-XC2287-96F80L AC
• Description: IC MCU 16BIT 768KB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: XC22xxr

Specifications of SAK-XC2287-96F80L AC

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: DMA, I²S, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Electrical Parameters
Bus Cycle Control with the READY Input
The duration of an external bus cycle can be controlled by the external circuit using the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
An asynchronous READY signal puts no timing constraints on the input signal but incurs
a minimum of one waitstate due to the additional synchronization stage. The minimum
duration of an asynchronous READY signal for safe synchronization is one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next bus cycle is controlled by READY, an active READY signal must be disabled
before the first valid sample point in the next bus cycle. This sample point depends on
the programmed phases of the next cycle.
Data Sheet
110
V2.1, 2008-08