UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 906

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Electrical
specifica-
tions
Develop-
ment tool
Instruction
set list
Function
Subclock
oscillator
characteristics
Data retention
characteristics
AC
characteristics
Bus timing
(multiplexed
bus mode)
Bus timing
(separate bus
mode)
I
A/D converter
Programming
characteristics
RX850,
RX850 Pro
Instruction set
2
C bus mode
Details of
Function
The subclock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main clock
oscillator.
Particular care is therefore required with the wiring method when the subclock is
used.
For the resonator selection and oscillator constant, customers are requested to
either evaluate the oscillation themselves or apply to the resonator manufacturer
for evaluation.
Shifting to STOP mode and restoring from STOP mode must be performed within
the rated operating range.
If the load capacitance exceeds 50 pF due to the circuit configuration, bring the
load capacitance of the device to 50 pF or less by inserting a buffer or by some
other means.
When operating at f
setup waits.
When operating at f
setup waits, and data waits.
At the start condition, the first clock pulse is generated after the hold time.
The system requires a minimum of 300 ns hold time internally for the SDA0n
signal (at V
falling edge of SCL0n.
If the system does not extend the SCL0n signal low hold time (t
maximum data hold time (t
The high-speed mode I
this case, set the high-speed mode I
conditions.
• If the system does not extend the SCL0n signal’s low state hold time:
• I If the system extends the SCL0n signal’s low state hold time:
Do not set (read/write) alternate-function ports during A/D conversion; otherwise
the conversion resolution may be degraded.
When writing initially to shipped products, it is counted as one rewrite for both
“erase to write” and “write only”.
Example (P: Write, E: Erase)
Shipped product ⎯⎯→P→E→P→E→P: 3 rewrites
Shipped product →E→P→E→P→E→P: 3 rewrites
To purchase the RX850 or RX850 Pro, first fill in the purchase application form
and sign the license agreement.
Do not specify the same register for general-purpose registers reg1 and reg3.
t
Transmit the following data bit to the SDA0n line prior to the SCL0n line release
(t
SU:DAT
Rmax
. + t
≥ 250 ns
SU:DAT
IHmin
. of SCL0n signal) in order to occupy the undefined area at the
= 1,000 + 250 = 1,250 ns: Normal mode I
XX
XX
> 20 MHz, be sure to insert address hold waits and address
> 20 MHz, be sure to insert address hold waits, address
2
C bus can be used in the normal-mode I
HD:DAT
) needs to be satisfied.
2
Cautions
C bus so that it meets the following
APPENDIX E LIST OF CAUTIONS
2
C bus specification).
LOW
2
C bus system. In
), only the
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