UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 883

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Watchdog
timer 2
function
Real-time
output
function
(RTO)
A/D
converter
Function
WDTM2 register To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop
WDTE register
RTBLn, RTBHn
registers
RTPMn register
RTPCn register Set the RTPEGn, BYTEn, and EXTRn bits only when RTPOEn bit = 0.
Realtime output
operation
Initialization
RTBHn, RTBLn
registers
ANI0 to ANI15
pins
ADA0M0
register
Details of
Function
the internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP
bit cannot be set to 1, set the WDCS23 bit to 1 (2
can be stopped in the IDLE1, IDLW2, sub-IDLE, and subclock operation modes).
When a value other than “ACH” is written to the WDTE register, an overflow
signal is forcibly output.
When a 1-bit memory manipulation instruction is executed for the WDTE register,
an overflow signal is forcibly output.
To intentionally generate an overflow signal, write a value other than “ACH” to the
WDTE register only once, or write data to the WDTM2 register only twice.
However, when the watchdog timer 2 is set to stop operation, an overflow signal
is not generated even if data is written to the WDTM2 register only twice, or a
value other than “ACH” is written to the WDTE register only once.
The read value of the WDTE register is “9AH” (which differs from written value
“ACH”).
When writing to bits 6 and 7 of the RTBHn register, always write 0.
Accessing the RTBLn and RTBHn registers is prohibited in the following statuses.
For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
After setting the real-time output port, set output data to the RTBLn and RTBHn
registers by the time a realtime output trigger is generated.
By enabling the real-time output operation (RTPCn.RTPOEn bit = 1), the bits
enabled to real-time output among the RTPn0 to RTPn5 signals perform realtime
output, and the bits set to port mode output 0.
If real-time output is disabled (RTPOEn bit = 0), the real-time output pins (RTPn0
to RTPn5) all output 0, regardless of the RTPMn register setting.
In order to use this register as the real-time output pins (RTPn0 to RTPn5), set
these pins as real-time output port pins using the PMC and PFC registers.
Prevent the following conflicts by software.
• Conflict between real-time output disable/enable switching (RTPOEn bit) and
• Conflict between writing to the RTBHn and RTBLn registers in the real-time
Before performing initialization, disable real-time output (RTPOEn bit = 0).
Once real-time output has been disabled (RTPOEn bit = 0), be sure to initialize
the RTBHn and RTBLn registers before enabling real-time output again (RTPOEn
bit = 0 → 1).
Make sure that the voltages input to the ANI0 to ANI15 pins do not exceed the
rated values.
In particular if a voltage of AV
value of that channel becomes undefined, and the conversion values of the other
channels may also be affected.
Accessing the ADA0M0 register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
stopped
selected real-time output trigger.
output enabled status and the selected real-time output trigger.
stopped
REF0
or higher is input to a channel, the conversion
Cautions
n
APPENDIX E LIST OF CAUTIONS
/f
XX
is selected and the clock
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