SAK-XE164HN-24F80L AA Infineon Technologies, SAK-XE164HN-24F80L AA Datasheet - Page 15

• Manufacturer Part Number: SAK-XE164HN-24F80L AA
• Description: IC MCU 16BIT 192KB FLASH 100LQFP
• Manufacturer: Infineon Technologies
• Series: XE16xr

Specifications of SAK-XE164HN-24F80L AA

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 192KB (192K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LSQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 5
Pin
6
7
8
9
Data Sheet
Symbol
P7.0
T3OUT
T6OUT
TDO_A
ESR2_1
P7.3
EMUX1
U0C1_DOUT O2
U0C0_DOUT O3
TMS_C
U0C1_DX0F
P7.1
EXTCLK
BRKIN_C
P7.4
EMUX2
U0C1_DOUT O2
U0C1_SCLK
OUT
TCK_C
U0C0_DX0D
U0C1_DX1E
Pin Definitions and Functions (cont’d)
Ctrl.
O0 / I St/B
O1
O2
OH /
IH
I
O0 / I St/B
O1
IH
I
O0 / I St/B
O1
I
O0 / I St/B
O1
O3
IH
I
I
Type Function
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
Bit 0 of Port 7, General Purpose Input/Output
GPT12E Timer T3 Toggle Latch Output
GPT12E Timer T6 Toggle Latch Output
JTAG Test Data Output / DAP1 Input/Output
If DAP pos. 0 or 2 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
ESR2 Trigger Input 1
Bit 3 of Port 7, General Purpose Input/Output
External Analog MUX Control Output 1 (ADC1)
USIC0 Channel 1 Shift Data Output
USIC0 Channel 0 Shift Data Output
JTAG Test Mode Selection Input
If JTAG pos. C is selected during start-up, an
internal pull-up device will hold this pin low when
nothing is driving it.
USIC0 Channel 1 Shift Data Input
Bit 1 of Port 7, General Purpose Input/Output
Programmable Clock Signal Output
OCDS Break Signal Input
Bit 4 of Port 7, General Purpose Input/Output
External Analog MUX Control Output 2 (ADC1)
USIC0 Channel 1 Shift Data Output
USIC0 Channel 1 Shift Clock Output
DAP0/JTAG Clock Input
If JTAG pos. C is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
If DAP pos. 2 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
USIC0 Channel 0 Shift Data Input
USIC0 Channel 1 Shift Clock Input
XE164FN, XE164GN, XE164HN, XE164KN
15
XE166 Family / Value Line
General Device Information
V1.2, 2010-04