SAK-XC888-8FFI 5V AC Infineon Technologies, SAK-XC888-8FFI 5V AC Datasheet - Page 87
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SAK-XC888-8FFI 5V AC
Manufacturer Part Number
SAK-XC888-8FFI 5V AC
Description
IC MCU 8BIT FLASH 64-TQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAF-XC888CLM-6FFA_5V_AC.pdf
(144 pages)
Specifications of SAK-XC888-8FFI 5V AC
Core Processor
XC800
Core Size
8-Bit
Speed
103.2MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.75K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LFQFP
For Use With
B158-H8743-X-X-7600IN - KIT STARTER XC886/888
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000253412
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3.10
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC886/888 system reset. Hence, routine service of the WDT
confirms that the system is functioning properly. This ensures that an accidental
malfunction of the XC886/888 will be aborted in a user-specified time period.
In debug mode, the WDT is default suspended and stops counting. Therefore, there is
no need to refresh the WDT during debugging.
Features
•
•
•
•
•
The WDT is a 16-bit timer incremented by a count rate of
timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be
preset to a user-programmable value via a watchdog service access in order to modify
the watchdog expire time period. The lower 8 bits are reset on each service access.
Figure 28
Figure 28
Data Sheet
ENWDT
ENWDT_P
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of
Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
f
PCLK
shows the block diagram of the WDT unit.
Watchdog Timer
Logic
WDT Block Diagram
1:128
1:2
f
PCLK
WDTIN
/2 or
MUX
80
f
PCLK
/128
WDT Low Byte
Control
WDT
Overflow/Time-out Control &
Window-boundary control
Clear
f
PCLK
/2 or
Functional Description
WDT High Byte
WDTWINB
WDTREL
f
PCLK
XC886/888CLM
/128. This 16-bit
V1.2, 2009-07
FNMIWDT
WDTRST
.
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