SAF-XC878-13FFI 3V3 AA Infineon Technologies, SAF-XC878-13FFI 3V3 AA Datasheet - Page 101

• Manufacturer Part Number: SAF-XC878-13FFI 3V3 AA
• Description: IC MCU 8BIT FLASH 64-LQFP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAF-XC878-13FFI 3V3 AA

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 27MHz
• Connectivity: SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 52KB (52K x 8)
• Program Memory Type: FLASH
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000447276

3.16
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features
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Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 28
Data Sheet
Master and slave mode operation
– Full-duplex or half-duplex operation
Transmit and receive buffered
Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
Variable baud rate
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
clock
shows the block diagram of the SSC.
High-Speed Synchronous Serial Interface
94
Functional Description
XC87xCLM
V1.5, 2011-03