SAK-XC886-8FFA 5V AC Infineon Technologies, SAK-XC886-8FFA 5V AC Datasheet - Page 133
![IC MCU 8BIT FLASH 48-TQFP](/photos/16/13/161323/qfp48_sml.jpg)
SAK-XC886-8FFA 5V AC
Manufacturer Part Number
SAK-XC886-8FFA 5V AC
Description
IC MCU 8BIT FLASH 48-TQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAF-XC888CLM-6FFA_5V_AC.pdf
(144 pages)
Specifications of SAK-XC886-8FFA 5V AC
Core Processor
XC800
Core Size
8-Bit
Speed
103.2MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.75K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-TFQFP
Data Bus Width
8 bit
Data Ram Size
1.75 KB
Interface Type
UART, SSC
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
B158-H8743-X-X-7600IN - KIT STARTER XC886/888B158-H8576-X-0-7600IN - KIT EASY XC866B158-H8548-X-0-7600IN - KIT STARTER XC866
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
SP000210971
- Current page: 133 of 144
- Download datasheet (2Mb)
4.3.3
Table 49
XC886/888.
Table 46
Parameter
Pad operating voltage
On-Chip Oscillator
start-up time
Flash initialization time
RESET hold time
PLL lock-in in time
PLL accumulated jitter
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
2) RESET signal has to be active (low) until
3) PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.
Data Sheet
provides the characteristics of the power-on reset and PLL timing in the
Power-on Reset and PLL Timing
Power-On Reset and PLL Timing (Operating Conditions apply)
Symbol
V
t
t
t
t
D
OSCST
FINIT
RST
LOCK
PAD
P
V
CC 2.3
CC –
CC –
SR –
CC –
DDC
has reached 90% of its maximum value (typ. 2.5 V).
min. typ.
–
126
Limit Values
–
–
160
500
–
–
max.
–
500
–
–
200
0.7
Unit Test Conditions
V
ns
µs
µs
µs
ns
Electrical Parameters
1)
1)
1)
V
(10% – 90%) ≤
500µs
1)
1)3)
XC886/888CLM
DDP
rise time
1)2)
V1.2, 2009-07
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