SAF-XC866-4FRA BE Infineon Technologies, SAF-XC866-4FRA BE Datasheet - Page 72

• Manufacturer Part Number: SAF-XC866-4FRA BE
• Description: IC MCU 8BIT 12KB FLASH 38TSSOP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAF-XC866-4FRA BE

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.11.1
The baud-rate generator is based on a programmable 8-bit reload value, and includes
divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud
rates based on its input clock f
Figure 29
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (f
output of the prescaler (f
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See
The baud rate (f
• Input clock f
• Prescaling factor (2
• Fractional divider (STEP/256) defined by register FDSTEP
Data Sheet
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
f
PCLK
Prescaler
Baud-Rate Generator
Baud-rate Generator Circuitry
FDEN
PCLK
FDM
BR
f
DIV
) value is dependent on the following parameters:
MOD
clk
BRPRE
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
DIV
Fractional Divider
) if the fractional divider is disabled (FDEN = 0). For baud rate
Adder
) defined by bit field BRPRE in register BCON
FDRES
1
1
FDSTEP
PCLK
0
, see
f
MOD
Figure
‘0’
f
DIV
0
(overflow)
68
FDEN&FDM
10
11
01
00
10
00
01
11
29.
R
0
1
NDOV
Section
8-Bit Baud Rate Timer
8-Bit Reload Value
Functional Description
3.12.
V1.2, 2007-10
f
BR
XC866