R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 545
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 545 of 1694
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12. DDR2-SDRAM Interface (DBSC2)
12.5.2
SDRAM Command Issue
(1)
Basic Access
The DBSC2 stores in a queue the requests received via the SuperHyway bus. Request processing
is begun around the time of preceding precharge/activate processing, but processing completion is
in the order received in the queue.
When SDRAM initialization is completed, upon receiving a read/write request, a page miss occurs
with all banks in the closed state. Hence the DBSC2 first issues an activate (ACT) command, to
open the corresponding bank. After opening the bank, the read/write command of the SDRAM
corresponding to the read/write request is issued. At this time, the number of issued read/write
commands differs depending on the bus width and the request size (1/2/4/8/16/32 bytes), as
indicated in figure 12.5. For example, when performing 32-byte reading from the SuperHyway
bus with an external data bus width of 32 bytes, two read commands are executed. When issuing
the read command in the first cycle, data is read with a burst length of 4 (two DDR clock cycles),
so that it is necessary to wait until the third cycle to issue the second read command.
When access ends, the DBSC2 leaves the bank open, without using a precharge (PRE) command.
The bank is closed when (1) the following request is for the same bank with a different row
address; (2) there is an auto-refresh request; or (3) the user issues a precharge-all (PALL)
command using the SDRAM command control register, for self-refresh processing.
Thus in normal access other than self-refresh, the DBSC2 uses hardware for bank management, so
that except for the register settings upon initialization, the user need not execute control.
Further, the DBSC2 performs multi-bank operation of four banks. Hence the maximum number of
banks which can be opened simultaneously is four. Refer to section 12.5.6, Regarding Address
Multiplexing, for the correspondence between access addresses from the SuperHyway bus and
SDRAM bank/row addresses.
When using the SDRAM with a memory capacity of 1 Gbit or greater, refer to section 12.5.8,
Important Information Regarding Use of 8-Bank DDR2-SDRAM Products.
Rev.1.00 Jan. 10, 2008 Page 513 of 1658
REJ09B0261-0100
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