R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 375
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 375 of 1694
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10.7
10.7.1
When ICR0.LVLMODE is 0, IRL interrupt requests and level detection IRQ interrupt requests
that the INTC retains should be cleared in the interrupt handling routine because the CPU detects
after accepting interrupts. The IRQ interrupt sources (INTREQ) should also be cleared.
Canceling the IRL interrupt request and level detection IRQ interrupt request that the CPU accepts
should be notified to the external device in the interrupt handling routine. For example, output the
data that can identify the accepted level and pins to the GPIO pin, or read the specific address. In
this case, write to the GPIO register and the local bus space, and read the same address
continuously.
To clear an interrupt request that is retained in the INTC, the wait time that the CPU detects the
cleared interrupt request is required. To guarantee the wait time, write to INTMSK0, INTMSK1,
INTMSKCLR0, and INTMSKCLR1, and read from INTMSK0 continuously.
Usage Notes
Example of Handing Routine of IRL Interrupts and Level Detection IRQ
Interrupts when ICR0.LVLMODE = 0
request holding in the detection circuit
Instruct the external device to cancel
the IRQ/IRL level interrupt request by
using the GPIO output or writing to an
address in the local bus
Wait until the interrupt request signal
input on the IRL/IRQ pin is negated
and the INTC detects the negation
(at least 8 bus-clock cycles are
required)
and clear the IRQ interrupt source
Clear the IRQ/IRL level interrupt
level-encoded interrupt handling
Start of IRQ level-sense or IRL
Figure 10.6 Example of Interrupt Handling Routine
End of IRQ/IRL level
Interrupt handling
interrupt handling
1) Write to the GPIO register or local
2) Read from the address that has been
1) Set the corresponding bit in
2) Set the corresponding bit in
3) Read INTMSK0/1.
bus space.
written to.
INTMSK0/1 to 1.
INTMSKCLR0/1 to 1.
Rev.1.00 Jan. 10, 2008 Page 343 of 1658
10. Interrupt Controller (INTC)
REJ09B0261-0100
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