MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 431

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MCF5272VF66R2J

Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5272VF66R2J

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Table 19-6
19.6.3
R/W is programmed on a per-chip-select basis for use with SRAM and external peripheral write accesses.
It should be connected to the external peripheral or memory write enable signal.
R/W acts as a write strobe to external SRAM when the decoded chip select is configured for either of the
two SRAM/ROM modes. It is asserted during on-chip peripherals accesses and negated during on-chip
SRAM accesses.
Freescale Semiconductor
shows how BS[3:0] should be connected to DQMx for 16- and 32-bit SDRAM configurations.
Read/Write (R/W)
In 16-bit bus mode, longword accesses are performed as two sequential
word accesses.
MCF5272 ColdFire
16 Bit 32 Bit
BS3
BS2
NC
NC
5272
BS3
BS2
BS1
BS0
Table 19-6. Connecting BS[3:0] to DQMx
BS1 BS0 Access Size Data Located On
BS3 BS2 Access Type Data Located On
1
1
0
0
1
1
0
0
for 16-Bit Data Bus—SDRAM Cycles
for 16-Bit Data Bus—SRAM Cycles
Table 19-4. Byte Strobe Operation
Table 19-5. Byte Strobe Operation
DQMH
DQML
16 Bit
NC
NC
®
1
0
1
0
1
0
1
0
Integrated Microprocessor User’s Manual, Rev. 3
32 Bit (2 x 16) 32 Bit (1 x 32)
DQMH
DQMH
DQML
DQML
None
Word
None
Word
Byte
Byte
Byte
Byte
NOTE
SDRAM
D[31:24]
D[23:16]
D[31:16]
D[23:16]
D[31:24]
D[31:16]
DQM3
DQM2
DQM1
DQM0
Data Signals
D[31:24]
D[23:16]
D[15:8]
D[7:0]
Signal Descriptions
19-21

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