M30620FCPFP#U3C Renesas Electronics America, M30620FCPFP#U3C Datasheet - Page 389
![IC M16C MCU FLASH 100QFP](/photos/12/42/124208/m30620fcpfp_u3c_sml.jpg)
M30620FCPFP#U3C
Manufacturer Part Number
M30620FCPFP#U3C
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620FCPFP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCPFP#U3CM30620FCPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 389 of 423
- Download datasheet (5Mb)
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
24.9.2
24.9.2.1
24.9.2.2
24.9.2.3
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5)
register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
A value of a counter, while counting, can be read in TBi register at any time. “FFFFh” is read while reloading.
Setting value is read between setting values in TBi register at count stop and starting a counter.
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5)
register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this register is
read at the same time the counter is reloaded, the read value is always “FFFFh”. If the TBi register is read after
setting a value in it while not counting but before the counter starts counting, the read value is the one that has
been set in the register.
The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before
setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register while the TBiS bit = 1
(count starts), be sure to write the same value as previously written to the TM0D0, TM0D1, MR0, MR1, TCK0
and TCK1 bits and a 0 to the MR2 bit.
The IR bit in the TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or Timer Bi is overflowed. The factor of interrupt request can be determined by use
of the MR3 bit in the TBiMR register within the interrupt routine.
If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input and a
timer overflow occur at the same time, use another timer to count the number of times Timer B has overflowed.
To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and counting the
next count source after setting the MR3 bit to “1” (overflow).
Use the IR bit to detect only overflows. Use the MR3 bit only to determine the interrupt factor.
When a count is started and the first effective edge is input, an indeterminate value is transferred to the reload
register. At this time, Timer Bi interrupt request is not generated.
A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and Timer Bi
interrupt request may be generated between a count start and an effective edge input.
For pulse width measurement, pulse widths are successively measured. Use program to check whether the
measurement result is an “H” level width or an “L” level width.
Jan 10, 2006
Timer B
Timer B (Timer Mode)
Timer B (Event Counter Mode)
Timer B (Pulse Period/pulse Width Measurement Mode)
Page 372 of 390
24. Precautions
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