M30620FCPFP#U3C Renesas Electronics America, M30620FCPFP#U3C Datasheet - Page 235
![IC M16C MCU FLASH 100QFP](/photos/12/42/124208/m30620fcpfp_u3c_sml.jpg)
M30620FCPFP#U3C
Manufacturer Part Number
M30620FCPFP#U3C
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620FCPFP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCPFP#U3CM30620FCPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.30
Data input timing
Clock output
(CKPOL=0, CKPH=0)
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
Clock output
(CKPOL=1, CKPH=1)
Data output timing
17.1.4.1
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the
UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Figure 17.30 shows the Transmission and Reception Timing in Master Mode (Internal Clock).
Figure 17.31 shows the Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) while
Figure 17.32 shows the Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock).
Jan 10, 2006
Clock Phase Setting Function
Transmission and Reception Timing in Master Mode (Internal Clock)
Page 218 of 390
“H”
“L”
“H”
“L”
“H”
“L”
“H”
“L”
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
17. Serial Interface
D7
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