M30620FCPFP#U5C Renesas Electronics America, M30620FCPFP#U5C Datasheet - Page 134
![IC M16C MCU FLASH 128K 100QFP](/photos/12/41/124176/m30620fcpfp_u5c_sml.jpg)
M30620FCPFP#U5C
Manufacturer Part Number
M30620FCPFP#U5C
Description
IC M16C MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620FCPFP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Package
100PQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCPFP#U5CM30620FCPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 12.8
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
time of acceptance of an interrupt request, is even or odd. If the stack pointer
the PC are saved,16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 12.8 shows the
Operation of Saving Register.
NOTES:
1.When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the
Jan 10, 2006
U flag. Otherwise, it is the ISP.
Operation of Saving Register
(1) SP contains even number
[SP] − 5 (Odd)
[SP] − 4 (Even)
[SP] − 3(Odd)
[SP] − 2 (Even)
[SP] − 1(Odd)
[SP]
(2) SP contains odd number
[SP] − 5 (Even)
[SP] − 4(Odd)
[SP] − 3 (Even)
[SP] − 2(Odd)
[SP] − 1 (Even)
[SP]
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL
NOTES :
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
Address
Address
(Odd)
After registers are saved, the SP content is [SP] minus 4.
(Even)
: 8 low-order bits of PC
Page 117 of 390
FLGH
FLGH
Stack
Stack
FLGL
FLGL
PCM
PCM
PCL
PCL
PCH
PCH
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Sequence in which order
registers are saved
Sequence in which order
registers are saved
Finished saving registers
in two operations.
Finished saving registers
in four operations.
(2) Saved simultaneously,
(1) Saved simultaneously,
(3)
(4)
(1)
(2)
all 16 bits
all 16 bits
Saved, 8 bits at a time
(1)
is even, the FLG register and
12. Interrupt
(1)
, at the
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