MC9S12XDT256MAA Freescale Semiconductor, MC9S12XDT256MAA Datasheet - Page 758

• Manufacturer Part Number: MC9S12XDT256MAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 16KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.7.2
Read: Anytime
Write: Anytime when S12XDBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in
enabled by setting the comparator enable bit in the associated DBGXCTL control register.
The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
760
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
Field
3–0
W
R
These bits select the targeted next state whilst in State2, based upon the match event.
0
0
7
Debug State Control Register 2 (DBGSCR2)
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
= Unimplemented or Reserved
Figure 20-10. Debug State Control Register 2 (DBGSCR2)
0
0
6
Table 20-23. State2 —Sequencer Next State Selection
Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State
Figure 20-1
Match3 triggers to Final State....... Other matches have no effect
Table 20-22. DBGSCR2 Field Descriptions
Match3 triggers to State1....... Other matches have no effect
Match3 triggers to State3....... Other matches have no effect
Match2 triggers to State1..... Match3 trigger to Final State
Table 20-38
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
and described in
Any match triggers to Final State
Any match triggers to state1
Any match triggers to state3
dictate that in the case of simultaneous matches, the match
0
0
4
Description
Description
Reserved
Reserved
Section
SC3
0
3
20.3.2.8.1”. Comparators must be
SC2
0
2
Freescale Semiconductor
SC1
0
1
SC0
0
0