MC9S12DG128CFUE Freescale Semiconductor, MC9S12DG128CFUE Datasheet - Page 57

• Manufacturer Part Number: MC9S12DG128CFUE
• Description: IC MCU 128K FLASH 2K EE 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DG128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI/I2C/CAN
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 50 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor, Inc.
MC9S12DT128B Device User Guide — V01.09
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
R
C
P
MCU
C
S
VDDPLL
VDDPLL
Figure 2-3 PLL Loop Filter Connections
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.
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