MC9S12DG128CFUE Freescale Semiconductor, MC9S12DG128CFUE Datasheet - Page 2

• Manufacturer Part Number: MC9S12DG128CFUE
• Description: IC MCU 128K FLASH 2K EE 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DG128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI/I2C/CAN
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 50 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC9S12DT128B Device User Guide — V01.09
Revision History
Number
Version
V01.00
V01.01
V01.02
V01.03
V01.04
V01.05
V01.06
V01.07
V01.08
V01.09
Revision
12 Sep
16 Aug
23 Sep
31 Oct
23 July
27 Feb
18 Jun
12 Oct
4 Mar
8 July
Date
2001
2001
2001
2001
2002
2002
2002
2002
2002
2002
Effective
18 June
23 Sep
12 Sep
23 July
27 Feb
22 July
16 Aug
12 Oct
31 Oct
4 Mar
Date
2001
2001
2001
2001
2002
2002
2002
2002
2002
2002
Freescale Semiconductor, Inc.
For More Information On This Product,
Author
Go to: www.freescale.com
Initial version (parent doc v2.03 dug for dp256).
Updated version after review
Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections
Replaced Star12 by HCS12
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos
Increased VDD to 2.35V, removed min. oscillator startup
Removed Document order number except from Cover Sheet
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
Minor corrections in table 1-1 & section 1.5.1
Corrected register address mismatches in section 1.5.1
Removed document order no. from Revision History page
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing CAN1,
BDLC, IIC and/or Byteflight
Added oscillator clock connection to BDM in S12_CORE in fig 3-1
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations.
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
Description of Changes