MC68HC11K0CFUE4 Freescale Semiconductor, MC68HC11K0CFUE4 Datasheet - Page 48

• Manufacturer Part Number: MC68HC11K0CFUE4
• Description: MCU 8-BIT 768 RAM 4MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K0CFUE4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Central Processor Unit (CPU)
3.3.4 Stack Pointer (SP)
Technical Data
48
The stack pointer holds the 16-bit address of the next free location in the
M68HC11 CPU’s automatic program stack. This stack is a data structure
that grows downward from high memory to low memory. The stack can
be located anywhere in the address space and can be any size up to the
amount of memory available in the system. Most application programs
initialize the SP at the beginning of an application program with a load
stack (LDS) instruction. Thereafter, each time the CPU pushes a new
byte onto the stack, it decrements the SP. To pull a byte from the stack,
the CPU first increments the SP.
operations.
A jump-to-subroutine (JSR) or branch-to-subroutine (BSR) instruction
pushes the address of the instruction immediately after the JSR or BSR
onto the stack, least significant byte first. The last instruction of the
subroutine is a return-from-subroutine (RTS), which pulls the previously
stored return address from the stack and loads it into the program
counter. Execution then continues at this recovered return address.
When the processor recognizes an interrupt, it finishes the current
instruction, pushes the return address (the current value in the program
counter) onto the stack, pushes all of the CPU registers onto the stack,
and continues at the address specified by the vector for the interrupt.
The interrupt service routine ends with a return-from-interrupt (RTI)
instruction, which pulls the saved registers off the stack in reverse order.
Program execution resumes at the return address with all register
contents restored.
There are instructions that push and pull the A and B accumulators and
the X and Y index registers to preserve program context. For example,
push accumulator A onto the stack when entering a subroutine that uses
accumulator A, and pull accumulator A off the stack just before leaving
the subroutine, to ensure that the contents of that register will be the
same after returning from the subroutine as it was before starting the
subroutine.
Freescale Semiconductor, Inc.
For More Information On This Product,
Central Processor Unit (CPU)
Go to: www.freescale.com
Figure 3-2
is a summary of SP
M68HC11K Family
MOTOROLA