MC68HC11K0CFUE4 Freescale Semiconductor, MC68HC11K0CFUE4 Datasheet - Page 177

• Manufacturer Part Number: MC68HC11K0CFUE4
• Description: MCU 8-BIT 768 RAM 4MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K0CFUE4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

8.6.3 Serial Peripheral Data Register
M68HC11K Family
MOTOROLA
Address: $002A
The SPDR is used when transmitting or receiving data on the serial bus.
Only a write to this register initiates transmission or reception of a byte,
and this only occurs in the master device. At the completion of
transferring a byte of data, the SPIF status bit is set in both the master
and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun
and the loss of the byte that caused the overrun, the first SPIF must be
cleared by the time a second transfer of data from the shift register to the
read buffer is initiated.
A write to SPDR goes directly to the transmission shift register.
A read of the SPDR retrieves data from the read data buffer.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 8-5. Serial Peripheral Data Register (SPDR)
Bit 7
Bit 7
0
Serial Peripheral Interface (SPI)
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Bit 6
6
0
Bit 5
5
0
Bit 4
4
0
Bit 3
3
0
Serial Peripheral Interface (SPI)
Bit 2
2
0
Bit 1
1
0
Technical Data
SPI Registers
Bit 0
Bit 0
0
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