M30800SFP-BL#D5 Renesas Electronics America, M30800SFP-BL#D5 Datasheet - Page 59

• Manufacturer Part Number: M30800SFP-BL#D5
• Description: MCU 3/5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#D5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
Figure 8.4 System clock control registers 0 and 1
6
1 .
0
C
9
0 .
8 /
B
0
0
0
1
A
8
G
u
7
b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0
o r
S y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( N o t e 1 )
S y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( N o t e 1 )
. g
0 -
N o t e 5 : W h e n e n t e r i n g t h e p o w e r s a v i n g m o d e , t h e m a i n c l o c k i s s t o p p e d u s i n g t h i s b i t . T o s t o p t h e m a i n
N o t e 6 : W h e n t h i s b i t i s " 1 " , X
Note 1: Set bit 0 of the protect register (address 000A
Note 2: Changes to “1” when shifting from high-speed or middle-speed mode to stop mode or reset.
Note 3: When this bit is "1", X
Note 4: When the main clock is stopped, the main clock division register (address 000C
N o t e 1 : S e t b i t 0 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 A
N o t e 2 : W h e n o u t p u t t i n g B C L K ( b i t 7 o f p r o c e s s o r m o d e r e g i s t e r 0 i s " 0 " ) , s e t t h e s e b i t s t o " 0 0 " . W h e n
N o t e 3 : W h e n s e l e c t i n g f
N o t e 4 : C h a n g e s t o “ 1 ” w h e n s h i f t i n g t o s t o p m o d e o r r e s e t .
N o t e 7 : W h e n t h e m a i n c l o c k i s s t o p p e d , t h e m a i n c l o c k d i v i s i o n r e g i s t e r ( a d d r e s s 0 0 0 C
N o t e 8 : W h e n " 1 " h a s b e e n s e t o n c e , " 0 " c a n n o t b e w r i t t e n b y s o f t w a r e .
N o t e 9 : T o s e t C M 0 7 " 1 " f r o m " 0 " , f i r s t s e t C M 0 4 t o " 1 " , a n d a n o s c i l l a t i o n o f s u b c l o c k i s s t a b l e . T h e n s e t
N o t e 1 0 : f c
N o t e 1 1 : W h e n X c
u
1
0
p
0
, 2
0
2
0
c l o c k , s e t s y s t e m c l o c k s t o p b i t ( C M 0 7 ) t o " 1 " w h i l e a n o s c i l l a t i o n o f s u b c l o c k i s s t a b l e . T h e n s e t t h i s
b i t t o " 1 " .
u p t o X
This bit is remained in low speed or low power dissipation mode.
X
division by 8 mode.
o u t p u t t i n g A L E t o P 5
p o r t P 5
m o d e a n d b i t 7 o f t h e p r o c e s s o r m o d e r e g i s t e r 0 i s " 1 " .
d i v i s i o n b y 8 m o d e .
C M 0 7 . A l s o , t o s e t C M 0 7 " 0 " f r o m " 1 " , f i r s t s e t C M 0 5 t o " 1 " , a n d a n o s c i l l a t i o n o f m a i n c l o c k i s
s t a b l e . T h e n s e t C M 0 7 . D o n o t r e w r i t e C M 0 4 a n d C M 0 5 s i m u l t a n e o u s l y .
0
0
COUT
5
3 2
0
Page 46
i s n o t i n c l u d e d .
0
are high-inpedance.
O U T
3
f u n c t i o n i s n o t s e l e c t e d e v e n w h e n y o u s e t " 0 0 " i n m i c r o p r o c e s s o r o r m e m o r y e x p a n s i o n
0
I N
( " H " l e v e l ) v i a t h e f e e d b a c k r e s i s t a n c e .
- X c
O U T
C
B i t s y m b o l
B i t s y m b o l
Reserved bit
f o
, f
Reserved bit
C M 0 1
CM02
C M 0 3
C M 0 4
C M 0 5
C M 0 7
C M 1 0
C M 1 5
C M 0 0
C M 0 6
8
i s u s e d , s e t p o r t P 8
3
3
S y m b o l
C M 0
S y m b o l
C M 1
O U T
OUT
o r f
2
( b i t 5 a n d 4 o f p r o c e s s o r m o d e r e g i s t e r 0 i s " 0 1 " ) , s e t t h e s e b i t s t o " 0 0 " . T h e
9
3 2
i s " H " . A l s o , t h e i n t e r n a l f e e d b a c k r e s i s t a n c e r e m a i n s O N , s o X
is "H", and the internal feedback resistance is disabled. X
i n s i n g l e c h i p m o d e , m u s t u s e P 5
X C I N - X C O U T d r i v e c a p a c i t y
s e l e c t b i t ( N o t e 4 )
W a t c h d o g t i m e r f u n c t i o n
s e l e c t b i t
Clock output function
select bit (Note 2)
WAIT peripheral function
clock stop bit
Port XC select bit
Main clock (XIN-XOUT)
stop bit (Note 5, 6)
System clock select bit
(Note 9)
A l l c l o c k s t o p c o n t r o l b i t
( N o t e 3 )
X
s e l e c t b i t ( N o t e 2 )
I N
- X
O U T
B i t n a m e
B i t n a m e
d r i v e c a p a c i t y
6
a n d P 8
A d d r e s s
A d d r e s s
0 0 0 6
0 0 0 7
16
1 6
1 6
1 6
) to “1” before writing to this register.
) t o “ 1 ” b e f o r e w r i t i n g t o t h i s r e g i s t e r .
7
t o n o p u l l - u p r e s i s t a n c e w i t h t h e i n p u t p o r t .
W h e n r e s e t
W h e n r e s e t
0 : W a t c h d o g t i m e r i n t e r r u p t
1 : R e s e t ( N o t e 8 )
b1 b0
0 0 : I/O port P53
0 1 : fC output (Note 3)
1 0 : f8 output (Note 3)
1 1 : f32 output (Note 3)
0 : Do not stop peripheral clock in wait
1 : Stop peripheral clock in wait mode
0 : LOW
1 : HIGH
0 : I/O port
1 : X
0 : On
1 : Off (Note 7)
0 : X
1 : X
0 : Clock on
1 : All clocks off (stop mode) (Note 4)
Always set to
Always set to
0 8
2 0
mode
(Note 10)
CIN
IN
CIN
1 6
1 6
7
, X
-X
, X
a s i n p u t p o r t .
OUT
COUT
COUT
“0”
“0”
Function
F u n c t i o n
generation (Note 11)
8. Clock Generating Circuit
16
1 6
) is set to the
) i s s e t t o t h e
CIN
and
I N
R
i s p u l l e d
R
W
W