HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 867
HD64F2318VTE25
Manufacturer Part Number
HD64F2318VTE25
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2318VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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(4) Timing of On-Chip Supporting Modules
Table 20.7 Timing of On-Chip Supporting Modules
Condition A: V
Condition B: V
Item
I/O ports
TPU
8-bit timer
WDT
Output data delay time
Input data setup time
Input data hold time
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
Overflow output delay time
0 V, φ = 2 MHz to 20 MHz, T
T
0 V, φ = 2 MHz to 25 MHz, T
T
a
a
CC
CC
= –40°C to 85°C (wide-range specifications)
= –40°C to 85°C (wide-range specifications)
= 2.7 V to 3.6 V, AV
= 3.0 V to 3.6 V, AV
Single-edge
specification
Both-edge
specification
Single-edge
specification
Both-edge
specification
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PWD
PRS
PRH
TOCD
TICS
TCKS
TCKWH
TCKWL
TMOD
TMRS
TMCS
TMCWH
TMCWL
WOVD
CC
CC
= 2.7 V to 3.6 V, V
= 3.0 V to 3.6 V, V
a
a
= –20°C to 75°C (regular specifications),
= –20°C to 75°C (regular specifications),
Min
—
30
30
—
30
30
1.5
2.5
—
30
30
1.5
2.5
—
Condition A
Rev.7.00 Feb. 14, 2007 page 833 of 1108
Max
50
—
—
50
—
—
—
—
50
—
—
—
—
50
Section 20 Electrical Characteristics
ref
ref
= 2.7 V to AV
= 3.0 V to AV
Min
—
25
25
—
25
25
1.5
2.5
—
25
25
1.5
2.5
—
Condition B
Max
40
—
—
40
—
—
—
—
40
—
—
—
—
40
CC
CC
REJ09B0089-0700
Unit
ns
ns
ns
ns
ns
ns
t
t
ns
ns
ns
t
t
ns
cyc
cyc
cyc
cyc
, V
, V
SS
SS
Test
Conditions
Figure 20.13
Figure 20.14
Figure 20.15
Figure 20.16
Figure 20.18
Figure 20.17
Figure 20.19
= AV
= AV
SS
SS
=
=
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