HD64F3687FPIV Renesas Electronics America, HD64F3687FPIV Datasheet - Page 28

• Manufacturer Part Number: HD64F3687FPIV
• Description: MCU 3/5V 56K I-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687FPIV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 17.2 External Circuit Connections of I/O Pins ................................................................ 305
Figure 17.3 I
Figure 17.4 I
Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 320
Figure 17.6 Master Transmit Mode Operation Timing (2)......................................................... 320
Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 322
Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 323
Figure 17.9 Slave Transmit Mode Operation Timing (1) ........................................................... 324
Figure 17.10 Slave Transmit Mode Operation Timing (2) ......................................................... 325
Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 326
Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 326
Figure 17.13 Clocked Synchronous Serial Transfer Format....................................................... 327
Figure 17.14 Transmit Mode Operation Timing......................................................................... 328
Figure 17.15 Receive Mode Operation Timing .......................................................................... 329
Figure 17.16 Block Diagram of Noise Conceler ........................................................................ 329
Figure 17.17 Sample Flowchart for Master Transmit Mode ...................................................... 330
Figure 17.18 Sample Flowchart for Master Receive Mode ........................................................ 331
Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 332
Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 333
Figure 17.21 The Timing of the Bit Synchronous Circuit .......................................................... 335
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 338
Figure 18.2 A/D Conversion Timing.......................................................................................... 344
Figure 18.3 External Trigger Input Timing ................................................................................ 345
Figure 18.4 A/D Conversion Accuracy Definitions (1).............................................................. 347
Figure 18.5 A/D Conversion Accuracy Definitions (2).............................................................. 347
Figure 18.6 Analog Input Circuit Example ................................................................................ 348
Section 19 EEPROM
Figure 19.1 Block Diagram of EEPROM................................................................................... 350
Figure 19.2 EEPROM Bus Format and Bus Timing .................................................................. 352
Figure 19.3 Byte Write Operation .............................................................................................. 355
Figure 19.4 Page Write Operation .............................................................................................. 356
Figure 19.5 Current Address Read Operation............................................................................. 357
Figure 19.6 Random Address Read Operation ........................................................................... 358
Figure 19.7 Sequential Read Operation (when current address read is used)............................. 358
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Figure 20.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 362
Figure 20.2 Operational Timing of Power-On Reset Circuit...................................................... 366
Figure 20.3 Operational Timing of LVDR Circuit ..................................................................... 367
Rev.5.00 Nov. 02, 2005 Page xxvi of xxxii
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C Bus Formats ...................................................................................................... 318
C Bus Timing........................................................................................................ 318