M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 97
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
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R
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E
1
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Table 9.3 Settings of Interrupt Priority Levels
J
6
ILVL2 to ILVL0 bits
0
9.3.1 I Flag
9.3.2 IR Bit
9.3.3 ILVL2 to ILVL0 Bits and IPL
C
2
9
2 /
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (interrupt not requested).
The IR bit can be cleared to “0” by program. Note that do not write “1” to this bit.
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3 shows the settings of interrupt priority levels and Table 9.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. Therefore, they do not affect
one another.
0 .
B
0
0
· I flag is set to “1”
· IR bit is set to “1”
· interrupt priority level > IPL
8
0
000
001
010
011
100
101
110
111
G
4
J
7
a
o r
2
2
2
2
2
2
2
2
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0
6
7
C
2 /
Interrupt priority
, 8
page 75
M
level
1
6
C
2 /
f o
8
3
) B
8
5
Priority
order
High
Low
Table 9.4 Interrupt Priority Levels Enabled
000
001
010
011
100
101
110
111
IPL
2
2
2
2
2
2
2
2
by IPL
Interrupt levels 1 and above are enabled
All maskable interrupts are disabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
Enabled interrupt priority levels
9. Interrupts
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