M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 180
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
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M
R
R
1
e
E
. v
6
J
Figure 13.22 Single-phase Waveform Output Mode
0
C
2
9
2 /
0 .
B
8
0
0
0
G
(1) Free-running operation
(2) The base timer is reset when the base timer matches either following register
4
J
7
a
o r
0 -
The above applies under the following conditions.
. n
(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to "0")
(a) G1PO0
(b) G1BTRR (enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
u
The above applies under the following conditions.
2
p
3
Base timer
G1IRj bit
0
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value) and the INV bit is set to "0" (not
The UD1 to UD0 bits are set to "00
OUTC1j pin
Base timer
OUTC1j pin
G1IRj bit
inversed).
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value) and the INV
bit is set to "0" (not inversed).
The UD1 to UD0 bits are set to "00
, 1
0
(
M
2
1
0
0
6
7
C
2 /
j = 1 to 7
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
page 158
, 8
m: Setting value of the G1POj register
n: Setting value of either G1PO0 register or G1BTRR register
G1IRj bit: Bits in the G1IR register
(enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or
FFFF
0000
M
FFFF
0000
1
6
16
n+2
16
m
C
m
16
16
2 /
f o
8
3
) B
f
8
m
BT1
f
5
m
BT1
2
" (counter increment mode).
2
" (counter increment mode).
65536
Inverse
Inverse
n+2-m
n+2
f
f
BT1
65536-m
BT1
f
BT1
f
When setting to "0",
write "0" by program
BT1
Write "0" by program
if setting to "0"
Return to default output level
Inverse
Inverse
Return to default
output level
Inverse
13. Timer S
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