MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 8

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MOTOROLA
Num
27A
29A
30A
39A
46A
47A
47B
27
28
29
30
31
33
35
37
39
46
48
53
54
55
70
71
72
73
74
75
76
77
78
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time)
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
DS, CS Negated to Data In Invalid (Data In Hold)
DS, CS Negated to Data In High Impedance
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLKOUT Low to Data In High Impedance
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
RESET Assertion Time
RESET Rise Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
(V
DD
13,14
and V
Freescale Semiconductor, Inc.
12
For More Information On This Product,
Table A–6 AC Timing (Continued)
Characteristic
DDSYN
10
= 5.0 Vdc
Go to: www.freescale.com
9
7
7, 8
11
5%, V
7
7
SS
= 0 Vdc, T
Symbol
t
A
t
t
t
t
t
t
t
BRAGA
t
t
t
t
t
CLBAN
t
SCLDD
SCLDS
SCLDH
t
t
t
BELCL
t
t
t
t
RWAS
t
SNDN
t
GAGN
t
t
t
DOCH
CHDH
RADC
t
CLDH
DABA
BKHT
t
RSTA
RSTR
BKST
SNDI
SHDI
DADI
DICL
CLDI
RWA
AIST
AIHT
MSH
t
t
MSS
= T
GH
GA
L
to T
H
Min
10
90
55
10
25
10
10
20
)
—
—
—
—
—
—
—
5
0
0
8
1
1
2
1
5
0
0
8
8
0
4
1
M68HC16ZEC25/D
Max
50
45
60
35
19
27
23
19
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
Unit
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
ns
cyc
cyc
8