MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 19

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

M68HC16ZEC25/D
ADDR[23:0]
DATA[15:0]
DATA[15:0]
CLKOUT
ECLK
R/W
Num
NOTES:
CS
E10
E11
E12
E13
E14
E15
E1
E2
E3
E4
E5
E6
E7
E8
E9
1. All AC timing is shown with respect to 20% V
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
4. Chip select access time = t
ECLK Low to Address Valid
ECLK Low to Address Hold
ECLK Low to CS Valid (CS Delay)
ECLK Low to CS Hold
CS Negated Width
Read Data Setup Time
Read Data Hold Time
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
CS Negated to Data High Impedance
ECLK Low to Data Valid (Write)
ECLK Low to Data Hold (Write)
Address Access Time (Read)
Chip-Select Access Time (Read)
Address Setup Time
E1
(V
E11
E15
E3
DD
and V
Freescale Semiconductor, Inc.
Ecyc
2A
Figure A–15 ECLK Timing Diagram
For More Information On This Product,
Characteristic
Ecyc
DDSYN
– t
2
Table A–8 ECLK Bus Timing
3
EAD
– t
4
ECSD
= 5.0 Vdc
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– t
EDSR
– t
EDSR
1A
.
DD
5%, V
and 70% V
.
E14
E13
WRITE
SS
= 0 Vdc, T
DD
3A
levels unless otherwise noted.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
EDDW
EDHW
ECSD
ECSH
ECSN
EDSR
EDHR
ECDH
EACC
t
t
EDHZ
ECDZ
EACS
t
A
EAD
EAH
EAS
E6
= T
L
to T
READ
E4
Min
255
195
E2
E7
H
10
10
20
25
—
—
—
—
—
—
E12
5
0
5
)
1
E8
E9
Max
E5
100
1/2
40
40
—
—
—
—
—
—
—
—
—
1
2
MOTOROLA
E10
HC16 E CYCLE TIM
WRITE
Unit
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
ns
ns
ns
cyc
19