M30280F6HP#U7B Renesas Electronics America, M30280F6HP#U7B Datasheet - Page 298

• Manufacturer Part Number: M30280F6HP#U7B
• Description: IC M16C/28 MCU FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#U7B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
16.12 START/STOP Condition Detect Operation
e
E
1
NOTES:
. v
J
Figure 16.18 Start condition detection timing diagram
Figure 16.19 Stop condition detection timing diagram
Table 16.10 Start/Stop detection timing table
6
SCL release time
Setup time
Hold time
BB flag set/reset
time
0
Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. The SSC4
to SSC0 bits in the S2D0 register set the START/STOP conditions. The START/STOP condition can be
detected only when the input signal of the SCL
release time, the set-up time, and the hold time (see Table 16.10). The BB flag in the S10 register is set to
“1” when the START condition is detected and it is set to “0” when the STOP condition is detected. The BB
flag set and reset timing varies between standard clock mode and high-speed clock mode. See Table
16.10.
C
2
9
0 .
B
2 /
0
0
1. Unit : number of cycle for I
8
0
4
J
G
The SSC value is the decimal notation value of the SSC4 to SSC0 btis. Do not set “0” or odd
numbers to the SSC setting. The values in () are examples when the S2D0 register is set to “18
at V
7
a
o r
0 -
. n
u
2
3
IIC
0
p
, 1
0
(
= 4 MHz.
M
2
0
1
0
6
7
C
2 /
page 276
, 8
M
1
BB flag
SSC value + 1 cycle (6.25 s)
SSC value + 1 cycle < 4.0 s (3.25 s)
SSC value
SSC value - 1 +2 cycles (3.375 s)
6
BB flag
C
S
S
f o
2 /
DA
CL
S
S
8
2
2
2
3
2
DA
Standard clock mode
CL
) B
8
C system clock V
5
cycle < 4.0 s (3.0 s)
Setup
time
Setup
MM
time
S
IIC
CL
S
release time
and SDA
CL
release time
BB flag
set time
BB flag
reset time
Hold
time
MM
Hold
time
16. MULTI-MASTER I
met the following conditions: the SCL
4 cycles (1.0 s)
2 cycles (0.5 s)
2 cycles (0.5 s)
3.5 cycles (0.875 s)
High-speed clock mode
2
C bus INTERFACE
16
”