M30260F6AGP#U9A Renesas Electronics America, M30260F6AGP#U9A Datasheet - Page 333
![IC M16C/26A MCU FLASH 48K 48LQFP](/photos/12/39/123991/m30260f6agp_u9a_sml.jpg)
M30260F6AGP#U9A
Manufacturer Part Number
M30260F6AGP#U9A
Description
IC M16C/26A MCU FLASH 48K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Specifications of M30260F6AGP#U9A
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
M30260F6AGP#U9AM30260F6AGP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30260F6AGP#U9AM30260F6AGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
M30260F6AGP#U9AM30260F6AGP#U3A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
M
e
E
1
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J
6
0
C
19.8.2 Serial I/O (UART Mode)
2
9
0 .
B
2 /
0
0
19.8.1.1 Special Mode 1 (I
19.8.1.2 Special Mode 2
19.8.1.3 Special Mode 4 (SIM Mode)
6
2
A
When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to “0”
and wait for more than half cycle of the transfer clock before setting each condition generate bit
(STAREQ, RSTAREQ and STPREQ) from “0” to “1”.
If a low-level signal is applied to the P8
to "1" (three-phase output forcible cutoff by input on SD pin enabled), the P7
U1MAP bit in PACR register is “1”) and CLK
A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmis-
sion complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM
mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
0
F
2
e
G
0 -
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o r
1 .
2
0
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, 5
0
p
2
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0
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0
7
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page 314
2 /
6
, A
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6
2
C
3
C bus Mode)
2
2 /
9
6
, B
M
1
6
C
5
/NMI/SD pin when the IVPCR1 bit in the TB2SC register is set
2 /
_______ _____
6
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2
pins go to a high-impedance state.
_____
3
/RTS
2
/TxD1(when the
19. Usage Notes
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