M30260F6AGP#U9A Renesas Electronics America, M30260F6AGP#U9A Datasheet - Page 140
![IC M16C/26A MCU FLASH 48K 48LQFP](/photos/12/39/123991/m30260f6agp_u9a_sml.jpg)
M30260F6AGP#U9A
Manufacturer Part Number
M30260F6AGP#U9A
Description
IC M16C/26A MCU FLASH 48K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Specifications of M30260F6AGP#U9A
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M30260F6AGP#U9AM30260F6AGP#D3
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Quantity:
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M30260F6AGP#U9AM30260F6AGP#U3
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e
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1
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J
6
Figure 12.3.4. IDB0 Register, IDB1Register, DTT Register, and ICTB2 Register
0
C
2
9
0 .
B
2 /
0
0
6
2
A
0
F
Three-phase output buffer register(i=0,1)
Dead time timer
2
b7
NOTE:
b7
NOTES:
e
G
0 -
1. Use MOV instruction to write to this register.
2. Effective when the INV15 bit is set to “0” (dead time timer enable). If the INV15 bit is set to “1”, the dead time timer is
b
Timer B2 Interrupt Occurrences Frequency Set Counter
1. The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The value
NOTE:
o r
b6
1 .
2
b7 b6 b5
disabled and has no effect.
written to the IDB0 register aftera transfer trigger represents the output signal of each phase, and the next value written
to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the output signal of each
phase.
0
1. Use MOV instruction to write to this register.
, 5
u
0
b5
b5
p
If the INV01 bit is set to "1", make sure the TB2S bit also is set to "0" (timer B2 count stopped) when writing to
this register. If the INV01 bit is set to "0", although this register can be written even when the TB2S bit is set to
"1" (timer B2 count start), do not write synchronously with a timer B2 underflow.
2
(
0
b4
b4
M
0
7
1
b3
b3
b4
6
C
b2
b2
b3
page 121
2 /
b1
b1
6
, A
b0
b0
(1, 2)
M
Assuming the set value = n, upon a start trigger the timer starts
counting the count souce selected by the INV12 bit and stops
after counting it n times. The positive or negative phase
whichever is going from an inactive to an active level changes
at the same time the dead time timer stops.
Bit symbol
b0
(b7-b6)
1
f o
DWBi
DUBi
DVBi
DWi
6
DUi
DVi
Symbol
Symbol
If the INV01 bit is "0" (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow.
If the INV01 bit is "1" (ICTB2 counter count timing
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow that meets the
condition selected by the INV00 bit.
Nothing is assigned. When write, set to "0". When read, its content is
indeterminate.
C
IDB0
IDB1
DTT
3
2
2 /
9
6
Symbol
ICTB2
, B
U phase output buffer i
U phase output buffer i
V phase output buffer i
V phase output buffer i
W phase output buffer i
W phase output buffer i
Nothing is assigned. When write, set to "0". When read,
these contents are "0".
M
Bit name
1
6
Function
C
2 /
Function
6
Address
034A
034B
Address
034C
Address
034D
) T
16
16
16
16
(1)
Write the output level
0: Active level
1: Inactive level
When read, these bits show the three-phase
output shift register value.
(1)
After Reset
Indeterminate
When reset
When reset
00111111
00111111
Indeterminate
1 to 15
Function
Setting Range
2
2
1 to 255
Setting range
WO
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
WO
12. Timer
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