HD64F3694FPJV Renesas Electronics America, HD64F3694FPJV Datasheet - Page 294

• Manufacturer Part Number: HD64F3694FPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3694FPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 I
15.7
15.7.1
In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing
under the following condition 1 or 2, such conditions may not be output successfully. To avoid
this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check
the SCLO bit in the I
1. When the rising of SCL falls behind the time specified in section 17.6, Bit Synchronous
2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth
15.7.2
If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the
slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To
avoid this, set the WAIT bit in ICMR to 0.
Rev.5.00 Nov. 02, 2005 Page 264 of 418
REJ09B0028-0500
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
clocks, that is driven by the slave device
Usage Notes
Issue (Retransmission) of Start/Stop Conditions
WAIT Setting in I
2
C Bus Interface 2 (IIC2)
2
C control register 2 (IICR2) to confirm the fall of the ninth clock.
2
C Bus Mode Register (ICMR)