M38227ECFP Renesas Electronics America, M38227ECFP Datasheet - Page 25

• Manufacturer Part Number: M38227ECFP
• Description: IC 740 MCU EPROM 48K 80QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38227ECFP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD
• Number Of I /o: 49
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
nal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software
interrupt set by the BRK instruction. An interrupt occurs if the cor-
responding interrupt request and enable bits are “1” and the
interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
Table 10 Interrupt vector addresses and priority
Notes1: Vector addresses contain interrupt jump destination addresses.
22
Reset (Note 2)
INT
INT
Serial I/O
reception
Serial I/O
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR
CNTR
Timer 1
INT
INT
Key input
(Key-on wake-up)
ADT
A-D conversion
BRK instruction
Interrupt Source
1. The contents of the program counter and processor status
0
1
2
3
2: Reset function in the same way as an interrupt with the highest priority.
register are automatically pushed onto the stack.
0
1
Priority
10
11
12
13
14
15
16
17
6
7
9
1
2
3
4
5
8
Vector Addresses (Note 1)
FFFD
FFED
FFEB
FFDF
FFDD
FFFB
FFF3
FFEF
FFE9
FFE7
FFE5
FFE3
FFE1
FFF9
FFF7
FFF5
FFF1
High
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
FFDC
FFFC
FFF8
FFEE
FFEC
FFEA
FFDE
FFFA
FFF6
FFF4
FFF2
FFF0
FFE8
FFE6
FFE4
FFE2
FFE0
Low
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At reset
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At completion of serial I/O data
reception
At completion of serial I/O trans-
mit shift or when transmission
buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR
At detection of either rising or
falling edge of CNTR
At timer 1 underflow
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
At completion of A-D conversion
At BRK instruction execution
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
•When switching interrupt sources of an interrupt vector address
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Generating Conditions
Related register: Interrupt edge selection register (address 3A
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 34
Notes on interrupts
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit or the interrupt source select bit
Set the corresponding interrupt request bit to “0” after 1 or more
Set the corresponding interrupt enable bit to “1” (enabled).
to “1”.
instructions have been executed.
Interrupt Request
2. The interrupt disable flag is set and the corresponding
3. The interrupt jump destination address is read from the vec-
interrupt request bit is cleared.
tor table into the program counter.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
0
1
2
3
input
input
input
input
0
1
input
input
Timer X mode register (address 27
Timer Y mode register (address 28
MITSUBISHI MICROCOMPUTERS
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(Valid at falling)
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
Valid when A-D interrupt is se-
lected
Non-maskable software interrupt
3822 Group
Remarks
16
)
16
16
)
)
16
)