D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 339
D13008VXI25V
Manufacturer Part Number
D13008VXI25V
Description
MCU 3V 0K I-TEMP PB-FREE 100-TQF
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13008VXI25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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10.2.7
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically
transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP
Bits 7 to 0
NDER7 to NDER0
0
1
Bit
Initial value
Read/Write
7
to TP
Next Data Enable Register A (NDERA)
0
) on a bit-by-bit basis.
NDER7
R/W
7
0
Description
TPC outputs TP
(NDR7 to NDR0 are not transferred to PA
TPC outputs TP
(NDR7 to NDR0 are transferred to PA
7
to TP
NDER6
R/W
6
0
0
) on a bit-by-bit basis.
NDER5
R/W
7
7
5
0
to TP
to TP
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
10. Programmable Timing Pattern Controller (TPC)
0
0
NDER4
are disabled
are enabled
R/W
4
0
Rev.4.00 Aug. 20, 2007 Page 293 of 638
NDER3
R/W
3
0
7
to PA
7
to PA
NDER2
R/W
0
)
2
0
0
)
NDER1
R/W
REJ09B0395-0400
1
0
(Initial value)
NDER0
R/W
0
0
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