D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 304
D13008VXI25V
Manufacturer Part Number
D13008VXI25V
Description
MCU 3V 0K I-TEMP PB-FREE 100-TQF
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13008VXI25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 304 of 688
- Download datasheet (4Mb)
9. 8-Bit Timers
Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination
with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the
input capture input detected edge.
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
ICE Bit in
8TCSR1
(8TCSR3)
0
1
• When the compare match register function is used, the timer output priority order is: toggle
• If compare match A and B occur simultaneously, the output changes in accordance with the
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
0
1
• When the compare match register function is used, the timer output priority order is: toggle
• If compare match A and B occur simultaneously, the output changes in accordance with the
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Rev.4.00 Aug. 20, 2007 Page 258 of 638
REJ09B0395-0400
output > 1 output > 0 output.
higher-priority compare match.
output > 1 output > 0 output.
higher-priority compare match.
Bit 0
OS0
0
1
0
1
Bit 3
OIS3
0
1
0
1
Bit 2
OIS2 Description
0
1
0
1
0
1
0
1
Description
No change when compare match A occurs
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and falling edges
(Initial value)
(Initial value)
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