MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 4

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Features
2.2
The following list provides the performance parameters of the MCF5253 processor.
2.3
This section summarizes the features of the MCF5253 processor.
2.3.1
The ColdFire processor Version 2 (V2) core consists of two independent, decoupled, pipeline structures to
maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage
pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage
operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer
that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,
which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC data path with a dual-read-ported register feeding an arithmetic/logic unit
(ALU).
More features of the ColdFire V2 processor core include:
2.3.2
Table 1
4
Mnemonic
ATA
ADC
Block
•
•
•
•
•
•
•
•
•
•
An internal 1.2 V regulator to supply the CPU and PLL
Maximum 140 MHz operating core frequency
Operating temperature range of -40° – +85° C
Packaged in a 225 MAPBGA, 14 × 14 mm 0.8 mm pitch
Clock-doubled Version 2 microprocessor core
32-bit internal data bus, 16 bit external data bus
16 user-visible, 32-bit general-purpose registers
Supervisor/user modes for system protection
Vector base register to relocate exception-vector table
Optimized for high-level language constructs
shows an alphabetical listing of the modules in the processor.
Critical Performance Parameters
Chip-Level Features
Advanced Technology
Attachment Controller
Battery Level/Keypad
Analog/Digital
Converter
ColdFire CF2 Core
Module Features
Block Name
MCF5253 ColdFire
Connectivity
Peripheral
Analog Input
Functional
Grouping
Table 1. Digital and Analog Modules
®
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disc drives and ATAPI optical disc drives.
The six-channel ADC is based on the Sigma-Delta concept with 12-bit
resolution. Both the analog comparator and digital sections are integrated
in the MCF5253.
Microprocessor Product Brief, Rev. 1
Brief Description
Freescale Semiconductor