C8051F010-GQR Silicon Laboratories Inc, C8051F010-GQR Datasheet - Page 108
C8051F010-GQR
Manufacturer Part Number
C8051F010-GQR
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F01xr
Specifications of C8051F010-GQR
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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WEAKPUD
Bit7:
Bit6:
Bits5-1: UNUSED. Read = 00000b, Write = don’t care.
Bit0:
Example Usage of XBR0, XBR1, XBR2:
When selected, the digital resources fill the Port I/O pins in order (top to bottom as shown in
Table 15.1) starting with P0.0 through P0.7, and then P1.0 through P1.7, and finally P2.0
through P2.7. If the digital resources are not mapped to the Port I/O pins, they default to their
matching internal Port Register bits.
Example1: If XBR0 = 0x11, XBR1 = 0x00, and XBR2 = 0x40:
P0.0=SDA, P0.1=SCL, P0.2=CEX0, P0.3=CEX1, P0.4 … P2.7 map to corresponding Port I/O.
Example2: If XBR0 = 0x80, XBR1 = 0x04, and XBR2 = 0x41:
P0.0=CP0, P0.1=/INT0, P0.2 = CNVSTR, P0.3 … P2.7 map to corresponding Port I/O.
R/W
Bit7
0: Weak Pull-ups Enabled (except for Ports whose I/O are configured as push-pull)
1: Weak Pull-ups Disabled
0: Crossbar Disabled
1: Crossbar Enabled
CNVSTE: ADC Convert Start Input Enable Bit
0: CNVSTR unavailable at Port pin.
1: CNVSTR routed to Port Pin.
WEAKPUD: Port I/O Weak Pull-up Disable Bit
XBARE: Crossbar Enable Bit
XBARE
R/W
Bit6
Figure 15.5. XBR2: Port I/O CrossBar Register 2
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.7
R/W
Bit3
-
R/W
Bit2
-
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
R/W
Bit1
-
CNVSTE
R/W
Bit0
SFR Address:
Reset Value
00000000
0xE3
108
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