R5F21237JFP Renesas Electronics America, R5F21237JFP Datasheet - Page 270

• Manufacturer Part Number: R5F21237JFP
• Description: MCU 3/5V 48K+2K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21237JFP

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Table 14.33
i = 0 or 1,
Count Sources
Count Operations
PWM Waveform
Count Start Condition
Count Stop Conditions
Interrupt Request Generation
Timing
TRDIOA0, TRDIOB0 Pin
Functions
TRDIOC0, TRDIOD0, TRDIOA1
to TRDIOD1 Pin Functions
INT0 Pin Function
Read from Timer
Write to Timer
Selection Functions
j = either A, B, C or D
PWM3 Mode Specifications
Item
Page 248 of 501
f1, f2, f4, f8, f32, fOCO40M
The TRD0 register is incremented. (The TRD1 is not used.)
PWM period: 1/fk × (m + 1)
Active level width of TRDIOA0 output: 1/fk × (m - n)
Active level width of TRDIOB0 output: 1/fk × (p - q)
Write 1 (count starts) to the TSTART0 bit in the TRDSTR register.
• Write 0 (count stops) to the TSTART0 bit in the TRDSTR register
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• Compare match (the content in the TRDi register matches with the
• The TRD0 register overflows
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output
• Select the active level every pin.
• Buffer operation (refer to 14.3.2 Buffer Operation)
fk: Frequency of count source
m: Setting value in the TRDGRA0 register
n: Setting value in the TRDGRA1 register
p: Setting value in the TRDGRB0 register
q: Setting value in the TRDGRB1 register
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
stops at the compare match in the TRDGRA0 register.
The PWM output pin holds level after output change by the compare
match.
content in the TRDGRji register.)
Forced Cutoff)
TRDIOA0 output
TRDIOB0 output
m + 1
n + 1
p + 1
q + 1
p - q
Specification
(When “H” is selected for the active level)
m - n
14. Timers