M30280F6HP#D5 Renesas Electronics America, M30280F6HP#D5 Datasheet - Page 336

• Manufacturer Part Number: M30280F6HP#D5
• Description: IC M16C MCU FLASH 48K 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
18.7 Software Commands
1
e
E
Table 18.5 Software Commands
. v
6
J
SRD: Status register data (D
WA : Write address (However,even address)
WD : Write data (16 bits)
BA : Highest-order block address (However,even address)
xx : 8 high-order bits of command code (ignored)
Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing
a command code, 8 high-order bits (D
18.7.1 Read Array Command (FF
18.7.2 Read Status Register Command (70
X : Any even address in the user ROM area
0
C
Read array
Read status register
Clear status register
Block erase
Program
2
9
The read array command reads the flash memory.
Read array mode is entered by writing command code ‘xxFF
fied address can be read in 16-bit unit after the next bus cycle. The microcomputer remains in read array
mode until an another command is written. Therefore, contents of multiple addresses can be read con-
secutively.
The read status register command reads the status register.
By writing command code ‘xx70
cycle (Refer to 18.8 Status Register). Read an even address in the user ROM area. Do not execute this
command in EW mode 1.
2 /
0 .
B
8
0
0
0
G
4
J
7
a
o r
Command
0 -
. n
u
2
p
3
0
, 1
0
(
M
2
0
1
0
6
7
C
2 /
page 314
, 8
M
7
1
6
to D
C
2 /
f o
Mode
Write
Write
Write
Write
Write
0
8
)
3
) B
16
8
5
’ in the first bus cycle, the status register can be read in the second bus
15
First bus cycle
–D
16
Address
8
) are ignored.
WA
)
X
X
X
X
(D
16
xxFF
xx70
xx50
xx40
xx20
15
Data
)
to D
16
16
16
16
16
0
16
)
’ in the first bus cycle. Content of a speci-
Mode
Write
Write
Read
Second bus cycle
Address
WA
BA
18. Flash Memory Version
X
(D
xxD0
15
SRD
Data
WD
to D
16
0
)