MCF52274CLU120 Freescale Semiconductor, MCF52274CLU120 Datasheet - Page 38

• Manufacturer Part Number: MCF52274CLU120
• Description: MCU 32-BIT LCD TOUCH 176-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5227xr

Specifications of MCF52274CLU120

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 47
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LQFP
• Family Name: MCF5227x
• Device Core: ColdFire
• Device Core Size: 16b
• Frequency (max): 120MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/3.6V
• Operating Supply Voltage (min): 1.4/1.7/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
5.14
Table 30
5.15
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many
of the transfer attributes are programmable.
to the DSPI chapter of the MCF52277 Reference Manual for information on the modified transfer formats used for
communicating with slower peripheral devices.
38
1
2
3
4
Master Mode
Slave Mode
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the
odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
When in master mode, the baud rate is programmable in DCTARn[PBR] and DCTARn[BR].
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DS10
DS11
DS12
DS13
DS14
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
lists timer module AC timings.
Num
DMA Timer Timing Specifications
DSPI Timing Specifications
DSPI_SCK Cycle Time
DSPI_SCK Duty Cycle
DSPI_PCSn to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
T1
T2
DT0IN / DT1IN / DT2IN / DT3IN cycle time
DT0IN / DT1IN / DT2IN / DT3IN pulse width
Characteristic
MCF5227x ColdFire
Table 31. DSPI Module AC Timing Specifications
Table 30. Timer Module AC Timing Specifications
Table 31
Characteristic
provides DSPI timing characteristics for classic SPI timing modes. Refer
®
Microprocessor Data Sheet, Rev. 8
Symbol
t
t
t
SCK
CSC
ASC
—
—
—
—
—
—
—
—
—
—
—
(2 × 1/f
(2 × 1/f
(tsck ÷ 2) – 2.0
4 x 1/f
Min
SYS
SYS
–5
—
—
—
—
9
0
0
2
7
SYS
) – 2.0
) – 3.0
Min
3
1
1
(tsck ÷ 2) + 2.0
Max
20
18
—
—
—
—
—
—
—
—
—
5
4
Max
Freescale Semiconductor
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
t
CYC
CYC
Notes
2
3
4