MCF52274CLU120 Freescale Semiconductor, MCF52274CLU120 Datasheet - Page 22

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MCF52274CLU120

Manufacturer Part Number
MCF52274CLU120
Description
MCU 32-BIT LCD TOUCH 176-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5227xr
Datasheet

Specifications of MCF52274CLU120

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, LCD, PWM, WDT
Number Of I /o
47
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LQFP
Family Name
MCF5227x
Device Core
ColdFire
Device Core Size
16b
Frequency (max)
120MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5/1.8/2.5/3.3V
Operating Supply Voltage (max)
1.6/3.6V
Operating Supply Voltage (min)
1.4/1.7/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
176
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF52274CLU120
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1
2
Electrical Characteristics
22
Num
FB4
FB5
FB6
FB7
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see
Specifications,”
The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more
information.
Data Input Setup
Data Input Hold
Transfer Acknowledge (TA) Input Setup
Transfer Acknowledge (TA) Input Hold
for SD_CS[3:0] timing.
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
FB_CSn, FB_OE,
Table 13. FlexBus AC Timing Specifications (continued)
FB_BE/BWEn
MCF5227x ColdFire
Characteristic
FB_D[31:X]
FB_A[23:0]
FB_CLK
FB_R/W
FB_TS
FB_TA
Figure 9. FlexBus Read Timing
FB1
ADDR[31:X]
S0
®
FB2
Microprocessor Data Sheet, Rev. 8
NOTE
FB6
ADDR[23:0]
S1
DATA
Section 5.7.2.2, “DDR SDRAM AC Timing
FB4
Symbol
t
t
t
t
DVFBCH
CVFBCH
DIFBCH
CIFBCH
S2
FB7
FB5
Min
S3
3.5
0
4
0
FB3
Max
Freescale Semiconductor
Unit
ns
ns
ns
ns
Notes

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