DF2211CUNP24V Renesas Electronics America, DF2211CUNP24V Datasheet - Page 113
DF2211CUNP24V
Manufacturer Part Number
DF2211CUNP24V
Description
MCU 16BIT FLASH 3V 64K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2211CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
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Price
Company:
Part Number:
DF2211CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
- Current page: 113 of 758
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2.6.2
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation Field
• Register Field
• Effective Address Extension
• Condition Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Specifies the branching condition of Bcc instructions.
Basic Instruction Formats
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
op
Figure 2.11 Instruction Formats (Examples)
op
op
cc
EA(disp)
op
r n
r n
EA(disp)
r m
r m
Rev.7.00 Dec. 24, 2008 Page 57 of 698
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
BRA d:16, etc.
REJ09B0074-0700
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