MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 42

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical Characteristics
42
4
5
6
All timing is shown with respect to 20% V
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
(CPOL = 1)
(OUTPUT)
(CPOL = 0)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(INPUT)
NOTES:
(CPOL = 0)
(CPOL = 1)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
MISO
MOSI
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SCK
(INPUT)
SCK
NOTES:
SS
MISO
MOSI
SS
1
SCK
SCK
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
(1)
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.3
11
2
6
11
MSB IN
Preliminary—Subject to Change Without Notice
MSB OUT
Figure 19. SPI Master Timing (CPHA = 0)
Figure 20. SPI Master Timing (CPHA = 1)
2
4
5
6
2
7
MSB IN
MSB OUT
4
5
2
2
DD
2
(2)
7
5
4
and 70% V
(2)
5
4
BIT 6 . . . 1
BIT 6 . . . 1
11
DD
BIT 6 . . . 1
12
, unless noted; 100 pF load on all SPI pins. All timing
BIT 6 . . . 1
LSB IN
LSB OUT
LSB OUT
LSB IN
Freescale Semiconductor
12
3
3