MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 169

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MC9S08GT60CFD

Manufacturer Part Number
MC9S08GT60CFD
Description
MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08GT60CFD

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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11.2
Features of SCI module include:
11.3
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. During
normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The following describes each of the blocks of the SCI.
11.4
As shown in
SCI communications require the transmitter and receiver (which typically derive baud rates from
independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends
on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is
performed.
Freescale Semiconductor
Full-duplex, standard non-return-to-zero (NRZ) format
Double-buffered transmitter and receiver with separate enables
Programmable baud rates (13-bit modulo divider)
Interrupt-driven or polled operation:
— Transmit data register empty and transmission complete
— Receive data register full
— Receive overrun, parity error, framing error, and noise error
— Idle receiver detect
Hardware parity generation and checking
Programmable 8-bit or 9-bit character length
Receiver wakeup by idle-line or address-mark
Features
SCI System Description
Baud Rate Generation
Figure
11-2, the clock source for the SCI baud rate generator is the bus-rate clock.
BUSCLK
Figure 11-2. SCI Baud Rate Generation
BAUD RATE =
BAUD RATE GENERATOR
OFF IF [SBR12:SBR0] = 0
MC9S08GB/GT Data Sheet, Rev. 2.3
MODULO DIVIDE BY
(1 THROUGH 8191)
SBR12:SBR0
[SBR12:SBR0] × 16
BUSCLK
DIVIDE BY
16
Rx SAMPLING CLOCK
(16 × BAUD RATE)
Tx BAUD RATE
Features
169

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